1. Field of the Invention
Embodiments of the invention relate generally to methods for processing a substrate during semiconductor manufacturing. Specifically, embodiments of the invention relate to methods of treating a conductive seed layer prior to an electrochemical deposition process.
2. Description of the Related Art
Reliably producing nanometer-sized features is one of the key technologies for the next generation of semiconductor devices. The shrinking dimensions of circuits and devices have placed additional demands on processing capabilities. The multilevel interconnects that lie at the heart of integrated circuit technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to future success and to the continued effort to increase circuit density and quality of individual substrates.
Metallization of features formed on substrates has historically focused on various plating processes, including electroplating. A substrate having openings to be filled with metal is exposed to an electrolyte solution while a voltage bias is applied. Electrolyte reacts with the biased substrate, depositing metal thereon.
Currently, copper and copper alloys have become the metals of choice over aluminum for nanometer-sized interconnect technology. Copper has a lower electrical resistivity (about 1.7 μΩ-cm compared to about 3.1 μΩ-cm for aluminum), a higher current carrying capacity, and significantly higher electromigration resistance than aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has good thermal conductivity and is available in a highly pure form.
FIG. 1 is a structural view of a substrate 100 treated according to a prior art process. Substrate 100 has field regions 102 and openings, such as trenches 104, in the field regions. The openings are typically filled to form features having high aspect ratio geometry. Trenches 104 have been subjected to a prior art electroplating process to deposit metal 106 therein, and deposited metal covers field regions 102 as well. The prior art electroplating process has produced voids 108 in filled features deposited in the trenches 104. Voids 108 arise because as electroplating proceeds, metal deposits on the field, and on sidewalls of the openings close to the field, faster than in the bottoms of the trenches. This creates an overhang which eventually bridges across the trench, creating a void and preventing trenches from being filled with metal.
As circuit densities increase, the widths of vias, apertures, trenches, contacts, and other openings, as well as the dielectric layers between them, decrease to nanometer dimensions, whereas the thickness of the dielectric layers remain substantially constant. Therefore, the aspect ratios of the features typically increase as current densities increase. Many traditional deposition processes have difficulty filling nanometer-sized openings where the aspect ratio exceeds 4:1, and particularly where the aspect ratio exceeds 10:1. Therefore, there is much effort directed at the formation of substantially void-free, nanometer-sized features having high aspect ratio geometries.